Complementary Metal Oxide Semiconductor (CMOS) technology has recently evolved, in terms of both frequency and noise, where it is increasingly being used in radio frequency (RF) applications in the GHz frequency range. Currently, cutoff frequencies of over 50 GHz have been reported for 0.18 μm CMOS technology and are expected to reach as high as 100 GHz as feature size shrinks to 100 nm. This translates into CMOS circuit operating frequencies well into the GHz range, which covers the frequency range of numerous wireless products in use today, such as mobile phones, Global Positioning System (GPS), Bluetooth.
The large interest in RF CMOS is due to the advantages of using CMOS technology in terms of production cost, high-level integration and the ability to combine digital, analog and RF circuits on the same integrated circuit (IC) (i.e. chip).
Another application of RF CMOS is in the fabrication of Digital RF Processors or Digital Radio Processors (DRP). In the fabrication of DRPs and other CMOS ICs it is well known that process variation in the core transistor for RF-CMOS technology results from minute inherent inconsistencies among chips made even within a single batch made from a few wafers or even a single wafer. This variation presents a particularly vexing challenge for designers of highly integrated “systems on a chip” (SoC). Knowing the process corner for each die makes it possible for the designer to compensate for the RF/analog performance differences by “dialing” the correct setting for parameters that affect device performance. At present, the extent of process variation in a design is inferred, rather than directly observed, by measuring some analog parameter of the wafer, such as current or gain. Typically, the process variation is indirectly measured by physically probing several test pads placed at different locations on the wafer and measuring a current which is closely associated to an RF parameter.
Unfortunately, indirect and external measurement to deduce process variation requires additional costly equipment and steps in the manufacturing process resulting in longer test times and significantly higher costs. Using an external test equipment would be inconvenient or impossible at certain stages of IC lifecycle, such as after the IC is assembled or in customer hands.
In addition to the process corner effect on the performance of RF, analog and digital circuits, the temperature and voltage also have significant effects. However, the voltage and temperature changes are considered environmental and are variable in comparison to the relatively static process corner characteristics.
Therefore, it is desirable to have a mechanism that is capable of measuring the process corner for each die on a semiconductor wafer that doe not require additional equipment and lengthy test times as is the case with prior art solutions. The mechanism should be relatively easy to implement, incur minimal testing time and cost while enabling compensation of system performance by configuring correct parameter settings for each individual chip die. It would also be desirable to track the voltage and temperature effects on the circuit performance after manufacture.